With the rapid development of integrated circuits technologies, there has been a trend to reduce the scale of a device. Thus, semiconductor technologies have increased the integrated circuit density on a chip. The semiconductor devices manufactured in and on the semiconductor substrate are very closely spaced. The alignment, lithography technologies are more important than ever due to the density of the packing density is continuously increased. Especially, the tolerance of self-align contact process is degrade, it is because that the contact window is reduced by scaling down the dimension of the features formed on a wafer.
Many devices includes conductive lines or structure for performing certain function, such as a bit line contact and a storage node contact must all be formed in a DRAM unit cell. In addition, multi-level interconnections are widely used in the advanced semiconductor device. Each device requires interconnections for exchanging electrical signals from one device to another device. Specially, the high performance integrated circuits have multi-level connections separated by dielectric layers. As the feature of the circuits is shrinkage, the need for decreasing the electrical resistance associated with electrical connection or contact becomes more important than ever. The higher of the resistance, the slower is the circuits operating speed limited by the RC delay.
An interconnection can be formed by forming a metal in a trench of an isolation layer. Then, the metal layer is polishing by chemical mechanical polishing (CMP). However, the CMP process suffers an issue called "dishing effect". The dishing effect is generated when the CMP performs on the metal layer formed over openings having different width, The surface of the metal is recessed below the interlayer in a dish shape in wider opening. This is unexpected result. During the polish, the polish pad usually reaches into the material formed in wide opening to remove material within the recess resulting in dishing. In contrast, narrow openings are polished without any dishing. The dishing structure is generated over the wide opening region, the effect may be caused by the slurry and the polished pad reach into the wide opening.
FIG. 1 illustrates a semiconductor substrate 10 having a plurality of conductive structure 12 formed thereon with narrow gap 14a and wide gap 14b formed between the structures. The conductive structure 12 requires dielectric or isolation layer formed over the conductive structure 12. FIG. 2 illustrates the structure of FIG. 1 after a layer 16 of material is formed thereon. The resulting substrate thus has an uneven topography. The layer 16 has an upper surface, which has a profile which is dictated by the topography of the substrate. High surfaces 22 of the surface are located above the conductive structure and the surface has lower surfaces 24 in the region of the gaps 14a, 14b.
Turning to FIG. 3, a polishing step is carried out until the conductive structures 12 are exposed by chemical mechanical polishing (CMP). CMP causes the high surfaces 22 to be removed. However, some of the material of the lower surfaces 24 is also removed so that topography of the layer before polishing is reflected on the structure after polishing. An upper surface of the structure after polishing thus has a profile with a dish 18 over the wide gap region. Because the width of the gap is different, the dishing effect will occur, which is a characteristic of the chemical mechanical polishing. As a result, dielectric over the wide gap 14b results in more over polishing than other area.
Thus, it is desirable to minimize or reduce dishing during the chemical-mechanical polishing of a wide integrated circuit feature.